Reviews of The Art of Verification with Vera
"The first three chapters of The Art of Verification with Vera should be required reading for any new verification engineer. These chapters build a solid foundation of the concepts required to thoroughly verify any piece of logic."
Bruce Wile, IBM (Verification Guild)
The Art of Verification with
SystemVerilog Assertions
Learn how to writeSVA-based assertions
Learn the basics of formal verification (Model checking)
- Detailed explanation of Sequences, Properties and Assertion Layer Directives
- Explains Assertion Based Verification
- Assertions for common design problems
- identifying assertions for different designs
- A primer on practical model checking
As ASICs move beyond a few million gates into tens or hundreds of millions of gates, and development schedules continue to shrink, traditional verification techniques relying on procedural testbench languages are no longer sufficient. These verification environments are so complex that several productivity enhancements are needed.
Checkers and coverage monitors need to be more concisely specified, especially when describing behaviors that span multiple clock cycles. Bugs need to be more quickly isolated to decrease debugging time. Stimulus generation needs to be further automated to accelerate coverage closure. Assertions enable all these productivity improvements by concisely specifying temporal behaviors for checkers and coverage monitors, pin-pointing bugs closer to their source, and enabling formal model checking techniques to automate stimulus generation
