As ASICs move beyond a few million gates into tens or hundreds of millions of gates, and development schedules continue to shrink, traditional verification techniques relying on procedural testbench languages are no longer sufficient. These verification environments are so complex that several productivity enhancements are needed.
Checkers and coverage monitors need to be more concisely specified, especially when describing behaviors that span multiple clock cycles. Bugs need to be more quickly isolated to decrease debugging time. Stimulus generation needs to be further automated to accelerate coverage closure. Assertions enable all these productivity improvements by concisely specifying temporal behaviors for checkers and coverage monitors, pin-pointing bugs closer to their source, and enabling formal model checking techniques to automate stimulus generation
