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By: Faisal Haque,
Jonathan Michelson,
Khizar Khan
Soft Cover. 452 pages.
Published by Verification Central
Date published: September 2001
About the Authors
Faisal Haque has 20 years experience in high-level verification and design of complex networking hardware. He authored Inside PC Card: CardBus and PCMCIA Design, published by Butterworth-Heinneman. He is currently working at Cisco Systems designing and verifying complex systems. He received his bachelors in electrical engineering from the University of Notre Dame.
Jonathan Michelson has 9 years experience verifying complex designs and writing verification infrastructure tools. He was co-designer of a verification language and methodology at Silicon Graphics. He is currently at Cisco Systems designing and verifying complex systems. He received his bachelors and masters degrees in electrical engineering and computer science from the Massachusetts Institute of Technology.
Khizar Khan has 9 years of experience in high-level verification and developing verification infrastructures. At Sun Microsystems, he is contributing to the verification of next generation microprocessors. He received his bachelors in electrical engineering from the University of Rochester.
The Art of Verification with Vera covers the essential elements
of VERA with detailed examples demonstrating how the VERA
testbench tool and the OpenVera language can be harnessed to
effectively verify different types of designs. It helps the reader
understand critical verification issues and teaches how to expedite
and enhance functional design verification.
This book discusses a range of verification issues including test
case identification, stimulus generation, results checking, test
coverage and test regression. Theses concepts are used to
develop a verification strategy and a VERA testbench for a
common design. Each component of this testbench is discussed in
detail to demonstrate the methodologies presented.
Highlights include:
Comprehensive discussion of verification strategies for complex System-on-a-chip designs.
Identifying test cases and testbench components Strategies for stimulus generation
Monitors and result-checking strategies
How to Build complex testbenches with Vera
Using Veras classes to do automatic stimulus generators, transactors and monitors
Run-time constraints with Vera
A detailed testbench for the Ethernet MAC
Practical issues in ASIC Verification
Test space coverage versus code coverage
Debugging strategies
Regressions
