The Art of Verification with VERA


Learn the basics of verification

  • Basics of verification methodology
  • Structured test planning
  • Basics of object oriented programming
  • Basics of constrained random
  • Basics of VERA language
  • Building testbenches with VERA
  • A complete testbench and testplan for an Ethernet MAC

3 reviews for The Art of Verification with VERA

  1. Samir Planitkar (Author of Verilog HDL: A Guide to Digital Design and Synthesis)

    “This book presents a practical step-by-step approach to learning and using Vera. Vera topics are covered in a logical order with the most frequently used areas introduced first. I would highly recommend this book to anyone using Vera”.
    Samir Planitkar (Author of Verilog HDL: A Guide to Digital Design and Synthesis)

  2. Narayan Murgesan, Verification Engineer

    “This book opened up the complex world of design verification for me. The authors have done a terrific job by following a thorough bottom-up approach which explains not just the object oriented VERA hardware verification language, but also delves on various design verification strategies and methodologies. In my opinion, this book is a must read for all ASIC development folks as well as others who might be interested in learning more about design verification in general and/or VERA. I must admit that this book definitely increased my productivity and made me feel more comfortable with ASIC design verification.”
    Narayan Murgesan Verification Engineer

  3. Monis Rahman, ASIC Engineer

    I was browsing through the bookstore yesterday and saw a copy of “The Art of Verification With Vera” so I picked up a copy. I’ve just been glancing through it but was very impressed. It’s one of the best books I’ve seen on verification, very easy to read and well explained. Congratulations on an excellent job!
    Monis Rahman ASIC Engineer

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