Introduction to ASIC DesignThe ASIC Design FlowWhat Is Verification?Functional Verification FlowWhat Does the Testbench Do?Problems of VerificationHardware Verification Languages (HVLs)Ethernet Switch ExampleCreating the Test PlanTest Generation SchemesTransactorsLogging and Error CheckingFormal VerificationEthernet Media Access Controller SpecificationIdentifying the TestbenchesIdentifying the Test CasesTest Generation PoliciesTransactorsMonitorsLogging and Error CheckingSummaryProgram StructureNumbers and Data TypesOperators and ExpressionsControl StructuresFunctions and TasksArrays and Associative ArraysStringsFile I/OA Complex Program: A CPUConclusionEvent Versus Cycle-Based SimulationInterfacing With a Simple Design: Multiport RAMDealing With Multiple Clocks and Multiple InterfacesInterface Signal TypesInterface ArchitectureAutomatic Template GenerationStimulus and ResponseVirtual Ports and BindsRunning a Vera Program With a SimulatorGuidelines and TechniquesThe Complete Testbench Development FlowMAC Port DefinitionConclusionfork/join ConstructShadow VariablesMailboxesSemaphoresRegionsEventsMore Thread ControlSummaryWhat Is an Object?Objects in VeraIdentifying Classes and MethodsSummaryObject-Oriented KeywordsTesting in VeraStimulus GenerationStimulus Generation for MACVera Support for RandomsTypes of ConstraintsPre- and Post-RandomizePacking and UnpackingTest Creation StrategiesSummaryIntroduction to Inheritance and PolymorphismExtending a Class in VeraApplication of InheritancePolymorphismGuidelines for Using Inheritance and PolymorphismConclusionTransactorsInterfacing With the StimulusMAC Transactor: Interfacing With the DesignExtending the Functionality of the TransactorsInstantiating the Extended ClassConclusionGeneration PoliciesInterfaces to Other Components of the testbenchComponents of the Stimulus GeneratorSample CodeMain ProgramProviding for Corner CasesSummaryResult CheckingMonitoring StrategiesExample MAC Testbench OverviewMAC Monitor ImplementationMAC Packet Monitoring IssuesHost MonitorMII MonitorInstantiating the MonitorsSummaryBug RateCoverageRegressions and RegressibilitySummaryAvoidance Through Preventive ProgrammingPreventive Programming StylesThe Debugging ProcessKey debugging issuesSummary